下列序列检测器实现检测序列为“11101000”， 其verilog程序描述正确的是（）。

A、说明部分程序 module sequ_detect(//检测序列11101000 input clk, input reset_n, input data_in, output check_flag ); localparam s0 = 0, s1= 1, s2 = 2, s3 = 3, s4 = 4, s5 = 5, s6 = 6, s7 = 7, s8 = 8; reg [3:0] c_st,next_st;

B、主控时序过程程序 always @(posedge clk,negedge reset_n) if(!reset_n) c_st ＜= 0; else c_st＞ C、主控组合过程程序 always @* case(c_st) s0 : if(data_in==1) next_st = s1; else next_st = s0; s1 : if(data_in==1) next_st = s2; else next_st = s0; s2 : if(data_in==1) next_st = s3; else next_st = s0; s3 : if(data_in==0) next_st = s4; else next_st = s3; s4 : if(data_in==1) next_st = s5; else next_st = s0; s5 : if(data_in==0) next_st = s6; else next_st = s2; s6 : if(data_in==0) next_st = s7; else next_st = s1; s7 : if(data_in==0) next_st = s8; else next_st = s1; s8 : if(data_in==0) next_st = s0; else next_st = s1; default : next_st = s0; endcase

D、辅助过程程序 assign check_flag = (c_st == s8) ; endmodule